DMA is a method for direct communication between peripherals and memory. Direct communication is important in situations where data must be moved very rapidly between a peripheral and memory. Interrupt-initiated programmed processing of each data transfer would cost time and could possibly cause data to be lost. With DMA, no programming is involved in the actual transfer of data. Bytes are moved without program intervention between memory and peripheral via the bus.
A DMA controller is a specialized processor that transfers data between memory and peripheral while allowing the CPU to perform other tasks. Typically, the CPU first programs the registers associated with each channel of the DMA controller. The registers in the DMA controller are given a start address of a first buffer in memory where data can be read from or written to, the length of this buffer, and the direction of the data flow. A peripheral requesting a DMA transfer first signals the DMA controller via a DMA request line. The DMA controller, in turn, responds by returning a corresponding DMA acknowledge signal. The DMA controller then directs the transfers, asserting address and strobing lines, with the peripheral asserting or receiving data to or from memory. When the length field of the buffer in the DMA controller goes to zero and there is still data to be transferred, the DMA controller sends the peripheral a signal that the buffer in memory is full or empty, stopping the peripheral's activity. The DMA controller or peripheral also asserts a CPU interrupt signal. In response to the interrupt, the CPU reprograms the DMA controller, giving the DMA controller a start address of a subsequent buffer where data is to be read from or written to, the length of this buffer, and the direction of the data flow. After the DMA controller has been reprogrammed, data transfer resumes.
The DMA controller must interrupt the CPU whenever the length field of the buffer in the DMA controller goes to zero and there is still data to be transferred. This is undesirable for several reasons. CPU intervention during a DMA data transfer requires that the CPU be interrupted from performing other tasks. For example, when the main memory is used to do block transfers, several buffer addresses might be needed. This causes the CPU to be interrupted several times. Also, in situations where there is a very fast DMA, the CPU may not be able to respond to the interrupt within the defined amount of time, causing data to be lost.
An alternative method for DMA is using a peripheral which is a bus master. The bus master peripheral has several address and control lines which connect the peripheral to the memory. The address and control lines allow the bus master to access information regarding the location of buffers which need to be read or written to without interrupting the CPU. In order to support the address and control lines, a peripheral would typically require additional component packaging, additional pins, and additional pin holes on the system circuit board. This translates to an additional cost to the system and the elimination of valuable space on the system circuit board.
Another approach for DMA without requiring CPU intervention is the use of intelligent DMA controllers. Intelligent DMA controllers offer the additional functionality of being able to handle multiple buffers themselves. Different DMA controllers, however, offer varying degrees of flexibility. For example, some specialized DMA controllers have the ability to halt at a particular buffer or location in a buffer in memory and signal an error. Other specialized DMA controllers have the ability to put status information in separate data structures or the ability to return to the beginning or a mid-point in the buffer. Often, one is unaware of the types of peripherals that will be implemented on a system when a DMA controller is selected. Thus, the DMA controller may offer data transfer capability beyond system requirements or it may offer insufficient data transfer capability.
Thus, a DMA controller which is capable of performing a variety of data transfers without interrupting the processor is desired. The present invention overcomes the drawbacks of the prior art by providing an apparatus and method for permitting a peripheral device to achieve the functional benefits of a bus master without requiring the address and control lines required for a bus master.